The Universal Chiplet Interconnect Express (UCIe) specification is designed to foster a disaggregated die architecture ecosystem, prioritizing interoperability across devices with varying performance. To achieve this, the specification defines compliance mechanisms. Compliance Goals UCIe compliance testing aims to validate the mainband supported features of a Device Under Test (DUT) against a reference UCIe implementation. Supporting…

What is Low Power Mode in VLSI Design? In VLSI design, low power mode refers to techniques or states where a system or circuit consumes as little power as possible. Power consumption is a critical aspect of modern electronics, especially for mobile devices like smartphones, wearables, and IOT devices. Reducing power consumption helps in improving…

Abstract CHIPS Alliance has developed an open-source riscv-dv random instruction generator for RISC-V processor verification. This article focuses on the class riscv_asm_program_gen.sv and its various functions, which generate the complete RISC-V assembly program, which is then used to verify RISC-V IP. This class can also address any customization to RISC-V GPR or instruction. Introduction The…

Introduction Artificial intelligence (AI) and machine learning (ML) are transforming many industries, such as healthcare, automotive, and electronics. As AI and ML technologies continue to evolve, they need powerful Hardware to process huge amounts of data quickly and efficiently. Traditional computers cannot handle these tasks well, so special hardware is being designed. The hardware that…

Programming Language Interface (PLI) is an interface which makes it possible for many programming languages to be integrated and communicate with one another. PLI acts as a bridge between different programming languages, facilitating interoperability and enabling developers to take advantage of several languages in a single application. In this article, we will explore more details…

Compute eXpress Link (CXL) is an open standard that allows a) Host to access externally connected pool of DDR memory space with simple load/store commands at low latencies. b) A host server to expand its memory map to acquire DDR space statically or dynamically as per program requirements. c) Devices like GPGPU that sit outside the system to…

While Register Transfer Level (RTL) simulation plays a vital role in verifying the high-level functionality of a design, it is often insufficient to catch all potential issues. This is where gate-level simulation (GLS) steps in as an important verification step, providing a more detailed and realistic view of the design's behaviour before it is sent…

Onboard Charger (OBC) Integrated Circuits (ICs) are critical components in electric vehicles (EVs), responsible for managing power conversion and battery charging. Verifying these ICs is essential to ensure functionality, reliability, and compliance with automotive standards. This article discusses the key aspects of OBC IC verification, including methodologies, challenges, and best practices. 1. Role of Onboard…

What is AMS Verification: Analog Mixed Signal (AMS) refers to simulations that utilize both analog and digital solvers. In the context of integrated circuit (IC) design, AMS verification involves testing and validating analog and mixed-signal ICs as per the design requirements. AMS designs combine both analog components (e.g., amplifiers, filters, oscillators) and digital components (e.g.,…

AMS & DMS in VLSI Verification Analog Mixed Signal (AMS) and Digital Mixed Signal (DMS) are both crucial areas in the verification and validation of integrated circuits, but they differ significantly in their nature and the expertise required for each. Analog Mixed Signal (AMS) AMS refers to the combination of analog and digital components within…

Direct Programming Interface (DPI) is a mechanism that allows System Verilog to call functions or tasks written in C/C++ and vice versa. DPI enables the integration of custom C/C++ code with System Verilog, facilitating advanced verification tasks that are difficult or inefficient to achieve purely in HDL. Key Features Lightweight interface. No need for PLI/VPI (Programming Language Interface/Verilog Procedural Interface). Simplified interaction between hardware design and software simulation environments. Importance of DPI in ASIC Verification Enhanced Verification Capabilities: DPI allows the use of existing C/C++ models or libraries for complex computations and data handling. Performance Optimization: Enables faster execution of time-consuming algorithms compared…