ASIC Verification has largely shifted its focus from the legacy procedural approach of building test benches to the more advanced object-oriented layered test bench architecture. It was imperative to find

Verification is a complex process. It consumes about 80% of the time and effort that goes into a typical ASIC cycle. With the rise in complexity of designs and an

We all have had our share of moments when ‘someone’ or ‘something’ just drives us to our wit’s end. It could be a bug hard to catch and even fix

An insatiable hunger for smarter, sleeker and power efficient electronics has put tremendous pressure on research and implementation of ASICs that fit the bill. While ASIC design is continuously under

Challenges faced by the Verification industry Design engineers are already facing the heat owing to the unquenchable demands for faster, sleeker and smarter electronics. While they burn the midnight oil

SystemVerilog is primarily and extensively used as a Hardware Verification Language (HVL). Also known as Super Verilog, it encompasses Verilog, VHDL and OOPS (Object Oriented Programming) concepts. As the designs

Verification is a process that ensures that the given design functions as per specifications. When we use the word ‘functions’, we also imply that the timing, form factor and power

Modern Day Designs Technological advancements have touched and transformed almost every sphere of our lives. From the high-end satellites in space that give us accurate information on the weather, location,

What is ‘Artificial Intelligence’? Suddenly one begins to notice that our search engine knows about that red dress we have been drooling on or our weight loss goals are not

Why we need smarter testbenches? “Less is more” no longer holds true and everyone needs a faster, smarter, power efficient gadget in the blink of an eye (well almost!). There