ANALOG MIX-SIGNAL VERIFICATION (AMS)
What is AMS Verification: Analog Mixed Signal (AMS) refers to simulations that utilize both analog and digital solvers. In the context of integrated circuit (IC) design, AMS verification involves testing
A comprehensive overview of AMS and DMS in VLSI Verification
AMS & DMS in VLSI Verification Analog Mixed Signal (AMS) and Digital Mixed Signal (DMS) are both crucial areas in the verification and validation of integrated circuits, but they differ
Direct Programming Interface (DPI)
Direct Programming Interface (DPI) is a mechanism that allows System Verilog to call functions or tasks written in C/C++ and vice versa. DPI enables the integration of custom C/C++ code with System Verilog, facilitating advanced verification tasks that are difficult or inefficient to achieve
Verification Methodology Basics & UVM
ASIC Verification has largely shifted its focus from the legacy procedural approach of building test benches to the more advanced object-oriented layered test bench architecture. It was imperative to find
UVM Environment: An Introduction
Verification is a complex process. It consumes about 80% of the time and effort that goes into a typical ASIC cycle. With the rise in complexity of designs and an
The ‘Inconclusive’ Customer: From Our Sales Diaries
We all have had our share of moments when ‘someone’ or ‘something’ just drives us to our wit’s end. It could be a bug hard to catch and even fix
SystemVerilog Concepts: Polymorphism
An insatiable hunger for smarter, sleeker and power efficient electronics has put tremendous pressure on research and implementation of ASICs that fit the bill. While ASIC design is continuously under
SystemVerilog Concepts: All About Semaphores
Challenges faced by the Verification industry Design engineers are already facing the heat owing to the unquenchable demands for faster, sleeker and smarter electronics. While they burn the midnight oil
SystemVerilog and the OOPS Concepts
SystemVerilog is primarily and extensively used as a Hardware Verification Language (HVL). Also known as Super Verilog, it encompasses Verilog, VHDL and OOPS (Object Oriented Programming) concepts. As the designs
Verification and Augmented Verification
Verification is a process that ensures that the given design functions as per specifications. When we use the word ‘functions’, we also imply that the timing, form factor and power