ASIC Verification has largely shifted its focus from the legacy procedural approach of building test benches to the more advanced object-oriented layered test bench architecture. It was imperative to find…
Verification is a complex process. It consumes about 80% of the time and effort that goes into a typical ASIC cycle. With the rise in complexity of designs and an…
We all have had our share of moments when ‘someone’ or ‘something’ just drives us to our wit’s end. It could be a bug hard to catch and even fix…
An insatiable hunger for smarter, sleeker and power efficient electronics has put tremendous pressure on research and implementation of ASICs that fit the bill. While ASIC design is continuously under…
Challenges faced by the Verification industry Design engineers are already facing the heat owing to the unquenchable demands for faster, sleeker and smarter electronics. While they burn the midnight oil…
SystemVerilog is primarily and extensively used as a Hardware Verification Language (HVL). Also known as Super Verilog, it encompasses Verilog, VHDL and OOPS (Object Oriented Programming) concepts. As the designs…
Verification is a process that ensures that the given design functions as per specifications. When we use the word ‘functions’, we also imply that the timing, form factor and power…
Layered architecture refers to a design methodology that divides the functionality of an integrated circuit (IC) into distinct layers, each responsible for a specific aspect of the design. This approach…
In the ever-evolving landscape of semiconductor design, chiplets have emerged as a revolutionary paradigm, reshaping the architecture of system-on-chip (SoC) systems. Central to this transformation is the Bunch of Wires…
In the ever-evolving landscape of semiconductor design, chiplets have emerged as a revolutionary paradigm, reshaping the architecture of system-on-chip (SoC) systems. Central to this transformation is the Bunch of Wires…
The BoW (Bunch of Wires) PHY layer is the physical foundation for communication between chiplets in a multi-chiplet design (ODSA) using the BoW interface. The BoW PHY layer is responsible…