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VeriFast BoW

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VeriFast BoW

BoW - Bunch of Wire VIP

VeriFast BoW is an innovative Verification IP (VIP) solution designed to accelerate verification of System-on-Chip (SoC) designs that leverage Open Domain-Specific Architecture (ODSA) chiplet interconnect. It specifically targets the link layer to PHY on the Bunch of Wires (BoW) interface.

By adopting VeriFast BoW, you can significantly reduce verification cycle times for SoCs that integrate chiplets from various vendors. This enables you to rapidly assemble domain-specific products with minimal verification hurdles. VeriFast BoW offers a rich set of features to enhance your verification productivity, supporting both standard and custom SoC dis-aggregation protocols.

Overview

VeriFast BoW (Bunch of Wires) Verification IP is targeting ODSA protocol link layer adapter to Phy on BoW interface. Reduces verification cycle time for SoC’s opting for chiplets from multiple vendors that can be assembled into domain specific products. It offers multiple productivity features enabling users to achieve rapid verification. Supports custom as well as standard SoC dis-aggregation protocols.
  • Standard SV UVM methodology
  • Detailed verification plan
  • Availability of regression test suite
  • Reduces test development effort
  • Shorten verification cycle
  • Provides a comprehensive user API (callbacks).
  • Provides easy integration in IP and SoC environment
Deliverables
  • BoW BFMs for :
    • Transaction Layer
    • Link Layer
    • PHY Layer
  • Layered Monitors/checkers/scoreboard
  • Test Suite with integrated VIP UVM env
  • Test sequence libraries
  • Smoke/Directed/Random tests
  • Error scenario tests
  • Training misalignment scenario tests
  • Other protocol compliance tests
  • Testbench examples for full stack and partial
    stack verification.
Features
  • Compliant to ODSA Transaction and Link Layer Specification
    for BoW Interfaces and Bunch of Wires (BoW) PHY
    specification
  • Supports AXI4 interface profile
  • Supports AXI5, AXI5-Lite D-32 and AXI5-Lite D-64 interface
    profile
  • Support for user Interface profile definitions
  • Supports BoW interface, LPI interface and VW interface
  • Supports SECDED (Single bit Error Correction Double bit
    Error Detection)
  • Supports all BoW modes based on configuration
  • vIP Configurations:
    • Full stack (Bow Interface) / Partial stack (Phy bypass)
    • Slice - x1, x2, x4 Ser. Ratio - x4, x8, x16
    • Set as Requester/Responder
    • Device/Monitor mode
  • Supports link training at data link layer
  • Arbitration scheme for payload fetching
  • Packet generation with support for error injection
  • Supports flow control unit with credit management scheme
  • Supports virtual wire for the transaction layer
  • Message support up-to 8 types
  • Functional coverage model for complete BoW features
  • Built in checkers performing protocol checks at all layers
  • Debug messages and trace logs
Experience Cutting-Edge Verification Solutions Today!
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